With the advent of faster and more powerful computer processing engines, and the associated increasingly complex computer applications capable of taking advantage of these leaps in computer technology, graphic display systems are continually challenged to provide graphical information to the display screen in a fast and efficient manner. Failure to process the graphics associated with an application (program) results in slower overall performance and, often, frustration in the user who has come to expect higher levels of performance and quicker responses from each new generation of computer processor.
One aspect of providing an image to the display screen requires the updating and storage of a very large amount of data corresponding to the image displayed. This data is stored in a memory commonly referred to as the video frame buffer. Such data typically includes at least the color data for a picture element (pixel), usually defined by a combination of the three primary colors red, blue and green, and a pixel location on the display screen, such as in x-y Cartesian coordinates. Since a display screen may contain on the order of hundreds of thousands of pixels, the volume of data which is processed for a single image displayed on the display screen is huge. The speed at which the data is updated in the frame buffer is further compounded by the fact that an image is transmitted to the screen approximately 70 times per second.
Furthermore, before an image is written into the frame buffer, the entire frame buffer or portions of the frame buffer are cleared. That is, the memory unit which is to store the information for a pixel is cleared of the color information from the prior image before the pixel color information of the current image is written into the frame buffer. This way, the graphics system can ensure that the new image has been correctly stored for the new image in the frame buffer. A clear may be implemented by setting the pixel color information to a predefined color, such as black (wherein the bit information associated with pixel color is set to a predefined value, such as all zeros or all ones or some other known reference value).
FIG. 1 is a simplified illustrative figure of a video monitor 20 having a display screen 22 which displays an image 24, and the associated frame buffer memory array 26. The frame buffer memory array 26 typically resides in the frame buffer (not shown). Frame buffer memory array 26 stores pixel data 28 in a two dimensional array. As is well known in the art, pixel data has at least information associated with the color and location of each pixel which is displayed on display screen 22.
In the simplified illustration of FIG. 1, the pixel data 28 associated with the first pixel in the upper-most left-hand corner of the display screen 22, is shown to reside in the first row and first column of the frame buffer memory array 26, as indicated by arrow 30. The pixel data 28 associated with the pixel in the upper-most right-hand corner of the display screen 22 is shown to reside in the first row and last column of the frame buffer memory array 26, as indicated by arrow 32. Thus, it is seen that in this simplified illustrative example, pixel data for the first row of the display screen 22 resides in the first row of the frame buffer memory array 26. Pixel data associated with the second row of pixels of the display screen 22 would be stored in the corresponding second row of the frame memory buffer array 26, and so on for all pixels of the display screen 22. Pixel data associated with the last pixel of the display screen 22, located at the bottom right hand corner, of the display screen 24 would be stored in the corresponding Nth row, last column, of the frame memory buffer array 26.
One skilled in the art will appreciate that other video graphic systems may store pixel data 28 in a variety of manners and configurations which are quite different from the simplified illustrative example of FIG. 1, depending upon the specific architecture of the frame buffer memory and the graphics system. For example, a plurality of memory units may comprise the storage medium of the frame buffer. Or, a row of memory cells residing in the frame buffer memory array 26 may not correspond exactly to a row of pixels on the display screen 22, such that the pixel data 28 associated with one row of pixels on the display screen 22 may reside in different rows of the frame buffer memory array 26. Or, alternative technologies may store pixel data 28 in a frame buffer memory array system employing blocks that can be addressed by either Cartesian coordinates for graphics performance or by linear addressing for application convenience. Such a scheme is referred to as a “pseudo-linear” frame buffer. However, when the processor orders the transmission of image 24 to the display screen 22 in a typical rasterized video graphics display system, the pixel data 28 is assembled in a sequential order starting with the first pixel in the upper-most left-hand corner of the display screen 22 and ending with the last pixel located at the bottom right hand corner of the display screen 22.
Similarly, the video graphics system application which writes data into the frame buffer memory array 26 may write pixel data into the frame buffer in a sequential manner. Depending upon the specific architecture of the video graphics system, data writing to the frame buffer memory array 26 may be implemented sequentially through the entire sequence of pixels, as in the simplified system of FIG. 1, or portions of the pixel data 28 may be written concurrently to a plurality of memory arrays by a group of parallel video processors. However, even with a parallel video graphics processor system, those portions of the pixel data 28 written to any particular memory array occurs in a sequential manner or in some other type of ordered manner. The large number of individual pixels which comprise a video image 24 is so great that processing systems in use today can not physically process all pixel information simultaneously. Some degree of sequential processing of pixel data is required.
FIG. 2 is a simplified illustrative figure of a display screen 22 of FIG. 1 with a window 42 written over the top of a portion of image 24. Window 42 is shown as a region of the display screen 22 drawn by solid vertical lines. Typically, such a window 42 represents a graphical output from a second application which is running concurrently with the application which created image 24. The computer user may be interacting with this second application in a manner which only requires a portion of the display screen 22, as is well known in the art.
During execution of the second application, the second application may generate the window 42 for viewing on the display screen 22. Typically, the window 42 would then be overwritten onto the top of image 24. Pixel data associated with window 42 is determined by the processor (not shown) executing the second application and then the pixel data is written into the frame buffer memory array 26 (FIG. 1) in a region of the frame buffer memory array 26 defined, in part, by the location of the window 42 on display screen 22. However, prior to writing the pixel data 28 associated with window 42 into the region of the frame buffer memory array 26, the region to which the pixel data 28 is to be written is first cleared. Because of the sequential processing of pixel data 28, the required clear of the region of the frame buffer memory array 26 associated with window 42 may require a substantial amount of time (relative to the time frame that the video graphic system is operating on).
The substantial time period required for the clearing of pixel data 28 (FIG. 1) associated with window 42 may result in a slow-down in the overall performance of the video graphic system and an associated slow-down in the performance of all application programs running on the computer system. Prior art systems have taken a variety of approaches in an effort to speed up the process of clearing. One basic approach is to utilize a plurality of specially designed memory units for block writes. A non-limiting example of one such type of memory is the Sychronous Graphics Random Access Memory (SGRAM). However, the use of SGRAM to speed up the clear process has the disadvantage of increased cost and the low-availability of SGRAM memory parts from parts suppliers.
Other methods of improving the clearing process utilities algorithms designed to avoid actually updating all of the memory associated with each individual pixel that is to be cleared. These special algorithms rely on specialized hardware and/or specialized software to hide the fact that the contents of a frame buffer do not match exactly what is displayed on the screen. Hence, these special algorithm methods require a certain degree of complexity to implement. Also, the specialized algorithms often have undesirable visual artifacts under certain “corner case” conditions, as is well known in the art. Therefore, these specialized fast clear algorithms have the disadvantage of requiring special hardware to execute the very complex algorithms and the disadvantage of the corner case problems associated with the undesirable visual artifacts.
Another method for improving clearing employs special memory configurations having a clear bit and a separate color register. These special memory configurations employ a single bit per pixel to indicate a clear condition to avoid writing all the bits that represent a pixel in the frame buffer 62 (FIG. 3). If the clear bit for a pixel is set, the color in the separate color register is transmitted to the display screen 20 in place of the contents of the frame buffer 62.
Because of the importance associated with the speed of a video graphics system, a heretofore unaddressed need exists in the industry for a way to better address the aforementioned deficiencies and inadequacies in clearing pixel data.